SYSTEM nios_0 { System_Wizard_Version = "5.10"; System_Wizard_Build = "176"; WIZARD_SCRIPT_ARGUMENTS { device_family = "CYCLONE"; clock_freq = "50000000"; generate_hdl = "1"; generate_sdk = "0"; do_build_sim = "0"; hardcopy_compatible = "0"; board_class = "de2"; CLOCKS { CLOCK clk { frequency = "50000000"; source = "External"; Is_Clock_Source = "0"; display_name = "clk"; pipeline = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } } hdl_language = "verilog"; device_family_id = "CYCLONEII"; view_master_columns = "1"; view_master_priorities = "0"; name_column_width = "680"; desc_column_width = "680"; bustype_column_width = "0"; base_column_width = "75"; clock_column_width = "80"; end_column_width = "75"; view_frame_window = "maximized"; do_log_history = "0"; RESETS { RESET reset_n { BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } } BOARD_INFO { class = "de2"; class_version = "1.0"; altera_avalon_epcs_flash_controller { reference_designators = "U30"; } altera_avalon_cfi_flash { reference_designators = "U20"; } reference_designators = "U30,U20"; initial_system_file = ""; device_family = "CYCLONEII"; REFDES U30 { base = "0x0"; } REFDES U20 { base = "0x0"; } CONFIGURATION FPGA_HW { reference_designator = "U30"; offset = "0x00000000"; menu_position = "0"; } } } MODULE cpu_0 { class = "altera_nios2"; class_version = "5.1"; iss_model_name = "altera_nios2"; HDL_INFO { PLI_Files = ""; Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_mult_cell.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v"; Synthesis_Only_Files = ""; } MASTER instruction_master { PORT_WIRING { PORT i_address { Is_Enabled = "1"; direction = "output"; type = "address"; width = "26"; } PORT i_read { Is_Enabled = "1"; direction = "output"; type = "read"; width = "1"; } PORT i_readdata { Is_Enabled = "1"; direction = "input"; type = "readdata"; width = "32"; } PORT i_readdatavalid { Is_Enabled = "1"; direction = "input"; type = "readdatavalid"; width = "1"; } PORT i_waitrequest { Is_Enabled = "1"; direction = "input"; type = "waitrequest"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Is_Instruction_Master = "1"; Is_Readable = "1"; Is_Writeable = "0"; Address_Group = "0"; Has_IRQ = "0"; Irq_Scheme = "individual_requests"; Interrupt_Range = "0-0"; Is_Enabled = "1"; Maximum_Burst_Size = "1"; Burst_On_Burst_Boundaries_Only = ""; Linewrap_Bursts = ""; Interleave_Bursts = ""; } } MASTER tightly_coupled_instruction_master_0 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Is_Instruction_Master = "1"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_instruction_master_1 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Instruction_Master = "1"; Is_Readable = "1"; Is_Writeable = "0"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_instruction_master_2 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Instruction_Master = "1"; Is_Readable = "1"; Is_Writeable = "0"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_instruction_master_3 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Instruction_Master = "1"; Is_Readable = "1"; Is_Writeable = "0"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER data_master { PORT_WIRING { PORT clk { Is_Enabled = "0"; direction = "input"; type = "clk"; width = "1"; } PORT d_address { Is_Enabled = "1"; direction = "output"; type = "address"; width = "26"; } PORT d_byteenable { Is_Enabled = "1"; direction = "output"; type = "byteenable"; width = "4"; } PORT d_irq { Is_Enabled = "1"; direction = "input"; type = "irq"; width = "32"; } PORT d_read { Is_Enabled = "1"; direction = "output"; type = "read"; width = "1"; } PORT d_readdata { Is_Enabled = "1"; direction = "input"; type = "readdata"; width = "32"; } PORT d_waitrequest { Is_Enabled = "1"; direction = "input"; type = "waitrequest"; width = "1"; } PORT d_write { Is_Enabled = "1"; direction = "output"; type = "write"; width = "1"; } PORT d_writedata { Is_Enabled = "1"; direction = "output"; type = "writedata"; width = "32"; } PORT jtag_debug_module_debugaccess_to_roms { Is_Enabled = "1"; direction = "output"; type = "debugaccess"; width = "1"; } } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "1"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "1"; Irq_Scheme = "individual_requests"; Interrupt_Range = "0-31"; Is_Enabled = "1"; Maximum_Burst_Size = "1"; Burst_On_Burst_Boundaries_Only = ""; } } MASTER data_master2 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "1"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "0"; Is_Enabled = "0"; } } MASTER tightly_coupled_data_master_0 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_data_master_1 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_data_master_2 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } MASTER tightly_coupled_data_master_3 { PORT_WIRING { } SYSTEM_BUILDER_INFO { Register_Incoming_Signals = "0"; Bus_Type = "avalon"; Data_Width = "32"; Max_Address_Width = "31"; Address_Width = "8"; Address_Group = "0"; Is_Data_Master = "1"; Is_Readable = "1"; Is_Writeable = "1"; Has_IRQ = "0"; Is_Enabled = "0"; Connection_Limit = "1"; Is_Channel = "1"; } } SLAVE jtag_debug_module { PORT_WIRING { PORT jtag_debug_module_address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "9"; } PORT jtag_debug_module_begintransfer { Is_Enabled = "1"; direction = "input"; type = "begintransfer"; width = "1"; } PORT jtag_debug_module_byteenable { Is_Enabled = "1"; direction = "input"; type = "byteenable"; width = "4"; } PORT jtag_debug_module_clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT jtag_debug_module_debugaccess { Is_Enabled = "1"; direction = "input"; type = "debugaccess"; width = "1"; } PORT jtag_debug_module_readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "32"; } PORT jtag_debug_module_reset { Is_Enabled = "1"; direction = "input"; type = "reset"; width = "1"; } PORT jtag_debug_module_resetrequest { Is_Enabled = "1"; direction = "output"; type = "resetrequest"; width = "1"; } PORT jtag_debug_module_select { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT jtag_debug_module_write { Is_Enabled = "1"; direction = "input"; type = "write"; width = "1"; } PORT jtag_debug_module_writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "32"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } } SYSTEM_BUILDER_INFO { Read_Wait_States = "1"; Write_Wait_States = "1"; Register_Incoming_Signals = "1"; Bus_Type = "avalon"; Data_Width = "32"; Address_Width = "9"; Accepts_Internal_Connections = "1"; Requires_Internal_Connections = "instruction_master,data_master"; Accepts_External_Connections = "0"; Is_Enabled = "1"; Address_Alignment = "dynamic"; Base_Address = "0x01000000"; Is_Memory_Device = "1"; Is_Readable = "1"; Is_Writeable = "1"; Is_Printable_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Has_IRQ = "0"; JTAG_Hub_Base_Id = "1118278"; JTAG_Hub_Instance_Id = "1"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } } PORT_WIRING { PORT jtag_debug_trigout { width = "1"; direction = "output"; Is_Enabled = "0"; } PORT jtag_debug_offchip_trace_clk { width = "1"; direction = "output"; Is_Enabled = "0"; } PORT jtag_debug_offchip_trace_data { width = "18"; direction = "output"; Is_Enabled = "0"; } PORT clkx2 { width = "1"; direction = "input"; Is_Enabled = "0"; visible = "0"; } } WIZARD_SCRIPT_ARGUMENTS { asp_debug = "0"; asp_core_debug = "0"; CPU_Architecture = "nios2"; do_generate = "1"; cpu_selection = "s"; CPU_Implementation = "small"; gui_include_tightly_coupled_instruction_masters = "0"; gui_num_tightly_coupled_instruction_masters = "1"; gui_omit_avalon_data_master = "0"; gui_include_tightly_coupled_data_masters = "0"; gui_num_tightly_coupled_data_masters = "1"; num_tightly_coupled_instruction_masters = "0"; num_tightly_coupled_data_masters = "0"; cache_has_dcache = "0"; cache_has_icache = "1"; cache_dcache_size = "2048"; cache_icache_size = "4096"; cache_dcache_line_size = "4"; cache_icache_line_size = "32"; cache_dcache_bursts = "0"; cache_icache_burst_type = "none"; cache_dcache_ram_block_type = "AUTO"; cache_icache_ram_block_type = "AUTO"; include_debug = "0"; include_trace = "0"; include_oci = "1"; include_third_party_debug_port = "0"; debug_level = "2"; oci_offchip_trace = "0"; oci_onchip_trace = "0"; oci_data_trace = "0"; oci_trace_addr_width = "7"; oci_num_xbrk = "0"; oci_num_dbrk = "0"; oci_dbrk_trace = "0"; oci_dbrk_pairs = "0"; oci_num_pm = "0"; oci_pm_width = "40"; oci_debugreq_signals = "0"; oci_trigger_arming = "1"; oci_embedded_pll = "1"; hardware_multiply_present = "1"; hardware_divide_present = "0"; gui_hardware_multiply_setting = "le_mul_fast_le_shift"; hardware_multiply_uses_les = "0"; hardware_multiply_omits_msw = "1"; hardware_multiply_impl = "le_mul"; gui_hardware_divide_setting = "0"; reset_slave = "cfi_flash_0/s1"; reset_offset = "0x00000000"; exc_slave = "sdram_0/s1"; exc_offset = "0x00000020"; break_slave = "cpu_0/jtag_debug_module"; break_offset = "0x00000020"; break_slave_override = ""; break_offset_override = "0x20"; legacy_sdk_support = "0"; altera_show_unreleased_features = "0"; full_waveform_signals = "0"; illegal_instructions_trap = "0"; gui_branch_prediction_type = "Automatic"; branch_prediction_type = "Static"; bht_ptr_sz = "8"; bht_index_pc_only = "0"; shift_rot_impl = "fast_le_shift"; mmu_present = "0"; process_id_num_bits = "10"; dtlb_ptr_sz = "7"; dtlb_num_ways = "4"; udtlb_num_entries = "6"; itlb_ptr_sz = "7"; itlb_num_ways = "4"; uitlb_num_entries = "4"; fast_tlb_miss_exc_slave = ""; fast_tlb_miss_exc_offset = "0x0"; cache_omit_dcache = "0"; cache_omit_icache = "0"; omit_instruction_master = "0"; omit_data_master = "0"; altera_internal_test = "0"; performance_counters_present = "0"; performance_counters_width = "32"; ras_ptr_sz = "4"; jtb_ptr_sz = "5"; ibuf_ptr_sz = "4"; always_encrypt = "1"; activate_model_checker = "0"; activate_monitors = "1"; activate_test_end_checker = "0"; activate_trace = "1"; clear_x_bits_ld_non_bypass = "1"; bit_31_bypass_dcache = "1"; always_bypass_dcache = "0"; hdl_sim_caches_cleared = "1"; consistent_synthesis = "0"; hbreak_test = "0"; allow_full_address_range = "0"; iss_trace_on = "0"; iss_trace_warning = "1"; iss_trace_info = "1"; iss_trace_disassembly = "0"; iss_trace_registers = "0"; iss_trace_instr_count = "0"; iss_software_debug = "0"; iss_software_debug_port = "9996"; iss_memory_dump_start = ""; iss_memory_dump_end = ""; Boot_Copier = "boot_loader_cfi.srec"; Boot_Copier_EPCS = "boot_loader_epcs.srec"; CONSTANTS { CONSTANT __nios_catch_irqs__ { value = "1"; comment = "Include panic handler for all irqs (needs uart)"; } CONSTANT __nios_use_constructors__ { value = "1"; comment = "Call c++ static constructors"; } CONSTANT __nios_use_small_printf__ { value = "1"; comment = "Smaller non-ANSI printf, with no floating point"; } CONSTANT nasys_has_icache { value = "1"; comment = "True if instruction cache present"; } CONSTANT nasys_icache_size { value = "4096"; comment = "Size in bytes of instruction cache"; } CONSTANT nasys_icache_line_size { value = "32"; comment = "Size in bytes of each icache line"; } CONSTANT nasys_icache_line_size_log2 { value = "5"; comment = "Log2 size in bytes of each icache line"; } CONSTANT nasys_has_dcache { value = "0"; comment = "True if instruction cache present"; } CONSTANT nasys_dcache_size { value = "2048"; comment = "Size in bytes of data cache"; } CONSTANT nasys_dcache_line_size { value = "4"; comment = "Size in bytes of each dcache line"; } CONSTANT nasys_dcache_line_size_log2 { value = "2"; comment = "Log2 size in bytes of each dcache line"; } } license_status = "ocp"; germs_monitor_id = ""; cpuid_sz = "1"; cpuid_value = "0"; remove_hardware_multiplier = "0"; inst_decode_in_submodule = "0"; register_dependency_in_submodule = "0"; source_operands_in_submodule = "0"; alu_in_submodule = "0"; stdata_in_submodule = "0"; shift_rot_2N_in_submodule = "0"; control_regs_in_submodule = "0"; M_inst_result_mux_in_submodule = "0"; dcache_load_aligner_in_submodule = "0"; hardware_divide_in_submodule = "0"; mult_result_mux_in_submodule = "0"; shift_rotate_in_submodule = "0"; register_file_write_data_mux_in_submodule = "0"; avalon_imaster_in_submodule = "0"; avalon_dmaster_in_submodule = "0"; avalon_load_aligner_in_submodule = "0"; mult_cell_in_submodule = ""; gui_illegal_instructions_trap = "0"; gui_illegal_memory_access_detection = "0"; illegal_memory_access_detection = "0"; gui_mmu_present = "0"; debug_simgen = "0"; } SYSTEM_BUILDER_INFO { Parameters_Signature = ""; Is_CPU = "1"; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII"; Default_Module_Name = "cpu"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "0"; Settings_Summary = "Nios II/s
  4-Kbyte Instruction Cache
  JTAG Debug Module "; } } SOFTWARE_COMPONENT altera_plugs_library { class = "altera_plugs_library"; class_version = "2.1"; WIZARD_SCRIPT_ARGUMENTS { CONSTANTS { CONSTANT PLUGS_PLUG_COUNT { value = "5"; comment = "Maximum number of plugs"; } CONSTANT PLUGS_ADAPTER_COUNT { value = "2"; comment = "Maximum number of adapters"; } CONSTANT PLUGS_DNS { value = "1"; comment = "Have routines for DNS lookups"; } CONSTANT PLUGS_PING { value = "1"; comment = "Respond to icmp echo (ping) messages"; } CONSTANT PLUGS_TCP { value = "1"; comment = "Support tcp in/out connections"; } CONSTANT PLUGS_IRQ { value = "1"; comment = "Run at interrupte level"; } CONSTANT PLUGS_DEBUG { value = "1"; comment = "Support debug routines"; } } } SYSTEM_BUILDER_INFO { Is_Enabled = "1"; } } SIMULATION { DISPLAY { SIGNAL aaa { format = "Logic"; name = "i_readdata"; radix = "hexadecimal"; } SIGNAL aab { format = "Logic"; name = "i_readdatavalid"; radix = "hexadecimal"; } SIGNAL aac { format = "Logic"; name = "i_waitrequest"; radix = "hexadecimal"; } SIGNAL aad { format = "Logic"; name = "i_address"; radix = "hexadecimal"; } SIGNAL aae { format = "Logic"; name = "i_read"; radix = "hexadecimal"; } SIGNAL aaf { format = "Logic"; name = "clk"; radix = "hexadecimal"; } SIGNAL aag { format = "Logic"; name = "reset_n"; radix = "hexadecimal"; } SIGNAL aah { format = "Logic"; name = "d_readdata"; radix = "hexadecimal"; } SIGNAL aai { format = "Logic"; name = "d_waitrequest"; radix = "hexadecimal"; } SIGNAL aaj { format = "Logic"; name = "d_irq"; radix = "hexadecimal"; } SIGNAL aak { format = "Logic"; name = "d_address"; radix = "hexadecimal"; } SIGNAL aal { format = "Logic"; name = "d_byteenable"; radix = "hexadecimal"; } SIGNAL aam { format = "Logic"; name = "d_read"; radix = "hexadecimal"; } SIGNAL aan { format = "Logic"; name = "d_write"; radix = "hexadecimal"; } SIGNAL aao { format = "Logic"; name = "d_writedata"; radix = "hexadecimal"; } SIGNAL aap { format = "Divider"; name = "base pipeline"; radix = ""; } SIGNAL aaq { format = "Logic"; name = "clk"; radix = "hexadecimal"; } SIGNAL aar { format = "Logic"; name = "reset_n"; radix = "hexadecimal"; } SIGNAL aas { format = "Logic"; name = "M_stall"; radix = "hexadecimal"; } SIGNAL aat { format = "Logic"; name = "F_pcb_nxt"; radix = "hexadecimal"; } SIGNAL aau { format = "Logic"; name = "F_pcb"; radix = "hexadecimal"; } SIGNAL aav { format = "Logic"; name = "D_pcb"; radix = "hexadecimal"; } SIGNAL aaw { format = "Logic"; name = "E_pcb"; radix = "hexadecimal"; } SIGNAL aax { format = "Logic"; name = "M_pcb"; radix = "hexadecimal"; } SIGNAL aay { format = "Logic"; name = "W_pcb"; radix = "hexadecimal"; } SIGNAL aaz { format = "Logic"; name = "F_vinst"; radix = "ascii"; } SIGNAL aba { format = "Logic"; name = "D_vinst"; radix = "ascii"; } SIGNAL abb { format = "Logic"; name = "E_vinst"; radix = "ascii"; } SIGNAL abc { format = "Logic"; name = "M_vinst"; radix = "ascii"; } SIGNAL abd { format = "Logic"; name = "W_vinst"; radix = "ascii"; } SIGNAL abe { format = "Logic"; name = "F_inst_ram_hit"; radix = "hexadecimal"; } SIGNAL abf { format = "Logic"; name = "F_issue"; radix = "hexadecimal"; } SIGNAL abg { format = "Logic"; name = "F_kill"; radix = "hexadecimal"; } SIGNAL abh { format = "Logic"; name = "D_kill"; radix = "hexadecimal"; } SIGNAL abi { format = "Logic"; name = "D_refetch"; radix = "hexadecimal"; } SIGNAL abj { format = "Logic"; name = "D_issue"; radix = "hexadecimal"; } SIGNAL abk { format = "Logic"; name = "D_valid"; radix = "hexadecimal"; } SIGNAL abl { format = "Logic"; name = "E_valid"; radix = "hexadecimal"; } SIGNAL abm { format = "Logic"; name = "M_valid"; radix = "hexadecimal"; } SIGNAL abn { format = "Logic"; name = "W_valid"; radix = "hexadecimal"; } SIGNAL abo { format = "Logic"; name = "W_wr_dst_reg"; radix = "hexadecimal"; } SIGNAL abp { format = "Logic"; name = "W_dst_regnum"; radix = "hexadecimal"; } SIGNAL abq { format = "Logic"; name = "W_wr_data"; radix = "hexadecimal"; } SIGNAL abr { format = "Logic"; name = "F_en"; radix = "hexadecimal"; } SIGNAL abs { format = "Logic"; name = "D_en"; radix = "hexadecimal"; } SIGNAL abt { format = "Logic"; name = "E_en"; radix = "hexadecimal"; } SIGNAL abu { format = "Logic"; name = "M_en"; radix = "hexadecimal"; } SIGNAL abv { format = "Logic"; name = "F_iw"; radix = "hexadecimal"; } SIGNAL abw { format = "Logic"; name = "D_iw"; radix = "hexadecimal"; } SIGNAL abx { format = "Logic"; name = "E_iw"; radix = "hexadecimal"; } SIGNAL aby { format = "Logic"; name = "E_valid_prior_to_hbreak"; radix = "hexadecimal"; } SIGNAL abz { format = "Logic"; name = "M_pipe_flush_nxt"; radix = "hexadecimal"; } SIGNAL aca { format = "Logic"; name = "M_pipe_flush_baddr_nxt"; radix = "hexadecimal"; } SIGNAL acb { format = "Logic"; name = "M_status_reg_pie"; radix = "hexadecimal"; } SIGNAL acc { format = "Logic"; name = "M_ienable_reg"; radix = "hexadecimal"; } SIGNAL acd { format = "Logic"; name = "intr_req"; radix = "hexadecimal"; } } } MASTER custom_instruction_master { PORT_WIRING { } SYSTEM_BUILDER_INFO { Bus_Type = "nios_custom_instruction"; Data_Width = "32"; Address_Width = "8"; Max_Address_Width = "8"; Base_Address = "N/A"; Is_Visible = "0"; Is_Custom_Instruction = "0"; Is_Enabled = "0"; } } } MODULE jtag_uart_0 { class = "altera_avalon_jtag_uart"; class_version = "5.1"; iss_model_name = "altera_avalon_jtag_uart"; SLAVE avalon_jtag_slave { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Is_Printable_Device = "1"; Address_Alignment = "native"; Address_Width = "1"; Data_Width = "32"; Has_IRQ = "1"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; JTAG_Hub_Base_Id = "0x04006E"; JTAG_Hub_Instance_Id = "1"; Connection_Limit = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "1"; } Base_Address = "0x01004000"; Address_Group = "0"; } PORT_WIRING { PORT clk { type = "clk"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT rst_n { type = "reset_n"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT av_chipselect { type = "chipselect"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT av_address { type = "address"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT av_read_n { type = "read_n"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT av_readdata { type = "readdata"; direction = "output"; width = "32"; Is_Enabled = "1"; } PORT av_write_n { type = "write_n"; direction = "input"; width = "1"; Is_Enabled = "1"; } PORT av_writedata { type = "writedata"; direction = "input"; width = "32"; Is_Enabled = "1"; } PORT av_waitrequest { type = "waitrequest"; direction = "output"; width = "1"; Is_Enabled = "1"; } PORT av_irq { type = "irq"; direction = "output"; width = "1"; Is_Enabled = "1"; } PORT dataavailable { Is_Enabled = "1"; direction = "output"; type = "dataavailable"; width = "1"; } PORT readyfordata { Is_Enabled = "1"; direction = "output"; type = "readyfordata"; width = "1"; } } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Iss_Launch_Telnet = "0"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = "
Write Depth: 64; Write IRQ Threshold: 8
Read Depth: 64; Read IRQ Threshold: 8"; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { write_depth = "64"; read_depth = "64"; write_threshold = "8"; read_threshold = "8"; read_char_stream = ""; showascii = "1"; read_le = "0"; write_le = "0"; altera_show_unreleased_jtag_uart_features = "0"; } SIMULATION { Fix_Me_Up = ""; DISPLAY { SIGNAL av_chipselect { name = "av_chipselect"; } SIGNAL av_address { name = "av_address"; radix = "hexadecimal"; } SIGNAL av_read_n { name = "av_read_n"; } SIGNAL av_readdata { name = "av_readdata"; radix = "hexadecimal"; } SIGNAL av_write_n { name = "av_write_n"; } SIGNAL av_writedata { name = "av_writedata"; radix = "hexadecimal"; } SIGNAL av_waitrequest { name = "av_waitrequest"; } SIGNAL av_irq { name = "av_irq"; } SIGNAL dataavailable { name = "dataavailable"; } SIGNAL readyfordata { name = "readyfordata"; } } INTERACTIVE_IN drive { enable = "0"; file = "_input_data_stream.dat"; mutex = "_input_data_mutex.dat"; log = "_in.log"; rate = "100"; signals = "temp,list"; exe = "nios2-terminal"; } INTERACTIVE_OUT log { enable = "1"; exe = "perl -- atail-f.pl"; file = "_output_stream.dat"; radix = "ascii"; signals = "temp,list"; } } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } } MODULE sdram_0 { class = "altera_avalon_new_sdram_controller"; class_version = "5.1"; iss_model_name = "altera_memory"; SLAVE s1 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "dynamic"; Has_IRQ = "0"; Maximum_Pending_Read_Transactions = "7"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; Is_Memory_Device = "1"; Address_Width = "22"; Data_Width = "16"; Simulation_Num_Lanes = "1"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00000000"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } PORT_WIRING { PORT zs_addr { direction = "output"; width = "12"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,,,,"; } } PORT zs_ba { direction = "output"; width = "2"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ","; } } PORT zs_cas_n { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT zs_cke { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT zs_cs_n { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT zs_dq { direction = "inout"; width = "16"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,,,,,,,,"; } } PORT zs_dqm { direction = "output"; width = "2"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ","; } } PORT zs_ras_n { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT zs_we_n { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT az_addr { Is_Enabled = "1"; direction = "input"; type = "address"; width = "22"; } PORT az_be_n { Is_Enabled = "1"; direction = "input"; type = "byteenable_n"; width = "2"; } PORT az_cs { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT az_data { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "16"; } PORT az_rd_n { Is_Enabled = "1"; direction = "input"; type = "read_n"; width = "1"; } PORT az_wr_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT za_data { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "16"; } PORT za_valid { Is_Enabled = "1"; direction = "output"; type = "readdatavalid"; width = "1"; } PORT za_waitrequest { Is_Enabled = "1"; direction = "output"; type = "waitrequest"; width = "1"; } } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Default_Module_Name = "sdram"; Disable_Simulation_Port_Wiring = "0"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = "4194304 x 16
Memory size: 8 MBytes
64 MBits "; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { register_data_in = "1"; sim_model_base = "1"; sdram_data_width = "16"; sdram_addr_width = "12"; sdram_row_width = "12"; sdram_col_width = "8"; sdram_num_chipselects = "1"; sdram_num_banks = "4"; refresh_period = "15.625"; powerup_delay = "100"; cas_latency = "3"; t_rfc = "70"; t_rp = "20"; t_mrd = "3"; t_rcd = "20"; t_ac = "5.5"; t_wr = "14"; init_refresh_commands = "2"; init_nop_delay = "0"; shared_data = "0"; starvation_indicator = "0"; tristate_bridge_slave = ""; is_initialized = "1"; sdram_bank_width = "2"; MAKE { TARGET delete_placeholder_warning { sdram_0 { Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; Is_Phony = "1"; Target_File = "do_delete_placeholder_warning"; } } TARGET sim { sdram_0 { Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)"; Command3 = "touch $(SIMDIR)/dummy_file"; Dependency = "$(ELF)"; Target_File = "$(SIMDIR)/dummy_file"; } } } } SIMULATION { Fix_Me_Up = ""; DISPLAY { SIGNAL a { name = "az_addr"; radix = "hexadecimal"; } SIGNAL b { name = "az_be_n"; radix = "hexadecimal"; } SIGNAL c { name = "az_cs"; } SIGNAL d { name = "az_data"; radix = "hexadecimal"; } SIGNAL e { name = "az_rd_n"; } SIGNAL f { name = "az_wr_n"; } SIGNAL g { name = "clk"; } SIGNAL h { name = "za_data"; radix = "hexadecimal"; } SIGNAL i { name = "za_valid"; } SIGNAL j { name = "za_waitrequest"; } SIGNAL k { name = "za_cannotrefresh"; suppress = "1"; } SIGNAL l { name = "CODE"; radix = "ascii"; } SIGNAL m { name = "zs_addr"; radix = "hexadecimal"; suppress = "0"; } SIGNAL n { name = "zs_ba"; radix = "hexadecimal"; suppress = "0"; } SIGNAL o { name = "zs_cs_n"; radix = "hexadecimal"; suppress = "0"; } SIGNAL p { name = "zs_ras_n"; suppress = "0"; } SIGNAL q { name = "zs_cas_n"; suppress = "0"; } SIGNAL r { name = "zs_we_n"; suppress = "0"; } SIGNAL s { name = "zs_dq"; radix = "hexadecimal"; suppress = "0"; } SIGNAL t { name = "zs_dqm"; radix = "hexadecimal"; suppress = "0"; } SIGNAL u { name = "zt_addr"; radix = "hexadecimal"; suppress = "1"; } SIGNAL v { name = "zt_ba"; radix = "hexadecimal"; suppress = "1"; } SIGNAL w { name = "zt_oe"; suppress = "1"; } SIGNAL x { name = "zt_cke"; suppress = "1"; } SIGNAL y { name = "zt_chipselect"; suppress = "1"; } SIGNAL z0 { name = "zt_lock_n"; suppress = "1"; } SIGNAL z1 { name = "zt_ras_n"; suppress = "1"; } SIGNAL z2 { name = "zt_cas_n"; suppress = "1"; } SIGNAL z3 { name = "zt_we_n"; suppress = "1"; } SIGNAL z4 { name = "zt_cs_n"; radix = "hexadecimal"; suppress = "1"; } SIGNAL z5 { name = "zt_dqm"; radix = "hexadecimal"; suppress = "1"; } SIGNAL z6 { name = "zt_data"; radix = "hexadecimal"; suppress = "1"; } SIGNAL z7 { name = "tz_data"; radix = "hexadecimal"; suppress = "1"; } SIGNAL z8 { name = "tz_waitrequest"; suppress = "1"; } } PORT_WIRING { PORT clk { Is_Enabled = "1"; direction = "input"; width = "1"; } PORT zs_addr { Is_Enabled = "1"; direction = "input"; width = "12"; } PORT zs_ba { Is_Enabled = "1"; direction = "input"; width = "2"; } PORT zs_cas_n { Is_Enabled = "1"; direction = "input"; width = "1"; } PORT zs_cke { Is_Enabled = "1"; direction = "input"; width = "1"; } PORT zs_cs_n { Is_Enabled = "1"; direction = "input"; width = "1"; } PORT zs_dq { Is_Enabled = "1"; direction = "inout"; width = "16"; } PORT zs_dqm { Is_Enabled = "1"; direction = "input"; width = "2"; } PORT zs_ras_n { Is_Enabled = "1"; direction = "input"; width = "1"; } PORT zs_we_n { Is_Enabled = "1"; direction = "input"; width = "1"; } } } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram_0.v, __PROJECT_DIRECTORY__/sdram_0_test_component.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } } MODULE tri_state_bridge_0 { class = "altera_avalon_tri_state_bridge"; class_version = "5.1"; SLAVE avalon_slave { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Bridges_To = "tristate_master"; Base_Address = "N/A"; Has_IRQ = "0"; IRQ = "N/A"; Register_Outgoing_Signals = "1"; Register_Incoming_Signals = "1"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } } MASTER tristate_master { SYSTEM_BUILDER_INFO { Bus_Type = "avalon_tristate"; Bridges_To = "avalon_slave"; } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Is_Bridge = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "0"; } } WIZARD_SCRIPT_ARGUMENTS { } } MODULE cfi_flash_0 { class = "altera_avalon_cfi_flash"; class_version = "5.1"; iss_model_name = "altera_avalon_flash"; HDL_INFO { } SLAVE s1 { PORT_WIRING { PORT data { width = "8"; is_shared = "1"; direction = "inout"; type = "data"; originally_shared = "1"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,"; } } PORT address { width = "22"; is_shared = "1"; direction = "input"; type = "address"; originally_shared = "1"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,,,,,,,,,,,,,,"; } } PORT read_n { width = "1"; is_shared = "1"; direction = "input"; type = "read_n"; originally_shared = "1"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT write_n { width = "1"; is_shared = "0"; direction = "input"; type = "write_n"; originally_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT select_n { width = "1"; is_shared = "0"; direction = "input"; type = "chipselect_n"; originally_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } } WIZARD_SCRIPT_ARGUMENTS { class = "altera_avalon_cfi_flash"; Supports_Flash_File_System = "1"; flash_reference_designator = "U20"; } SYSTEM_BUILDER_INFO { Bus_Type = "avalon_tristate"; Is_Nonvolatile_Storage = "1"; Is_Memory_Device = "1"; Address_Alignment = "dynamic"; Has_IRQ = "0"; Base_Address = "0x02000000"; Data_Width = "8"; Address_Width = "22"; Simulation_Num_Lanes = "1"; Convert_Xs_To_0 = "1"; Write_Wait_States = "160ns"; Read_Wait_States = "160ns"; Setup_Time = "40ns"; Hold_Time = "40ns"; Address_Span = "4194304"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } MASTERED_BY tri_state_bridge_0/tristate_master { priority = "1"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Make_Memory_Model = "1"; Is_Enabled = "1"; Instantiate_In_System_Module = "0"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Setup_Value = "40"; Wait_Value = "160"; Hold_Value = "40"; Timing_Units = "ns"; Unit_Multiplier = "1"; Size = "4194304"; MAKE { MACRO { CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_0_FLASHTARGET_TMP1:0=)"; CFI_FLASH_0_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)"; } MASTER cpu_0 { MACRO { BOOT_COPIER = "boot_loader_cfi.srec"; CPU_CLASS = "altera_nios2"; CPU_RESET_ADDRESS = "0x2000000"; } } TARGET delete_placeholder_warning { cfi_flash_0 { Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; Is_Phony = "1"; Target_File = "do_delete_placeholder_warning"; } } TARGET flashfiles { cfi_flash_0 { Command1 = "@echo Post-processing to create $(notdir $@)"; Command2 = "elf2flash --input=$(ELF) --flash=U20 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER) --outfile=$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x2000000 --end=0x23FFFFF --reset=$(CPU_RESET_ADDRESS) "; Dependency = "$(ELF)"; Target_File = "$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash"; } } TARGET sim { cfi_flash_0 { Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)"; Command3 = "touch $(SIMDIR)/dummy_file"; Dependency = "$(ELF)"; Target_File = "$(SIMDIR)/dummy_file"; } } TARGET programflash { cfi_flash_0 { All_Depends_On = "0"; Command1 = "nios2-flash-programmer --input=$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir de2 $(QUARTUS_PROJECT_DIR))/ $(JTAG_CABLE) --base=0x0 "; Dependency = "$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash"; Is_Phony = "1"; Target_File = "cfi_flash_0_programflash"; } } TARGET programflashnoelfdependency { cfi_flash_0 { All_Depends_On = "0"; Command1 = "nios2-flash-programmer --input=$(CFI_FLASH_0_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash_0.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir de2 $(QUARTUS_PROJECT_DIR))/ $(JTAG_CABLE) --base=0x0 "; Is_Phony = "1"; Target_File = "cfi_flash_0_programflashnoelf"; } } } } } MODULE timer_0 { class = "altera_avalon_timer"; class_version = "5.1"; iss_model_name = "altera_avalon_timer"; SLAVE s1 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Is_Printable_Device = "0"; Address_Alignment = "native"; Address_Width = "3"; Data_Width = "16"; Has_IRQ = "1"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "0"; } Base_Address = "0x00900000"; Address_Group = "0"; } PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "3"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "16"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "16"; } } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = "Timer with 1 ms timeout period."; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { always_run = "0"; fixed_period = "0"; snapshot = "1"; period = "1"; period_units = "ms"; reset_output = "0"; timeout_pulse_output = "0"; mult = "0.001"; } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } } MODULE sysid { class = "altera_avalon_sysid"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } SLAVE control_slave { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "32"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Address_Width = "1"; Data_Width = "32"; Base_Address = "0x00900020"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; Read_Latency = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Fixed_Module_Name = "sysid"; Top_Level_Ports_Are_Enumerated = "1"; View { Settings_Summary = "System ID (at last Generate):
76F8C268 (unique ID tag)
444790EC (timestamp: Thu Apr 20, 2006 @3:47 PM)"; Is_Collapsed = "1"; MESSAGES { } } Clock_Source = "clk"; } WIZARD_SCRIPT_ARGUMENTS { id = "1996014184u"; timestamp = "1145540844u"; MAKE { TARGET verifysysid { verifysysid { All_Depends_On = "0"; Command = "nios2-download $(JTAG_CABLE) --sidp=0x00900020 --id=1996014184 --timestamp=1145540844"; Is_Phony = "1"; Target_File = "dummy_verifysysid_file"; } } } } } MODULE uart_0 { class = "altera_avalon_uart"; class_version = "5.1"; iss_model_name = "altera_avalon_uart"; PORT_WIRING { PORT rxd { direction = "input"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT txd { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT cts_n { direction = "input"; width = "1"; Is_Enabled = "0"; } PORT rts_n { direction = "output"; width = "1"; Is_Enabled = "0"; } } SLAVE s1 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Is_Printable_Device = "1"; Address_Alignment = "native"; Address_Width = "3"; Data_Width = "16"; Has_IRQ = "1"; Read_Wait_States = "1"; Write_Wait_States = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "2"; } Base_Address = "0x00900040"; Address_Group = "0"; } PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "3"; } PORT begintransfer { Is_Enabled = "1"; direction = "input"; type = "begintransfer"; width = "1"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT dataavailable { Is_Enabled = "1"; direction = "output"; type = "dataavailable"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT read_n { Is_Enabled = "1"; direction = "input"; type = "read_n"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "16"; } PORT readyfordata { Is_Enabled = "1"; direction = "output"; type = "readyfordata"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "16"; } } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Iss_Launch_Telnet = "0"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = "8-bit UART with 115200 baud,
1 stop bits and N parity"; MESSAGES { } Is_Collapsed = "1"; } } SIMULATION { DISPLAY { SIGNAL a { name = " Bus Interface"; format = "Divider"; } SIGNAL b { name = "chipselect"; } SIGNAL c { name = "address"; radix = "hexadecimal"; } SIGNAL d { name = "writedata"; radix = "hexadecimal"; } SIGNAL e { name = "readdata"; radix = "hexadecimal"; } SIGNAL f { name = " Internals"; format = "Divider"; } SIGNAL g { name = "tx_ready"; } SIGNAL h { name = "tx_data"; radix = "ascii"; } SIGNAL i { name = "rx_char_ready"; } SIGNAL j { name = "rx_data"; radix = "ascii"; } } INTERACTIVE_OUT log { enable = "0"; file = "_log_module.txt"; radix = "ascii"; signals = "temp,list"; exe = "perl -- tail-f.pl"; } INTERACTIVE_IN drive { enable = "0"; file = "_input_data_stream.dat"; mutex = "_input_data_mutex.dat"; log = "_in.log"; rate = "100"; signals = "temp,list"; exe = "perl -- uart.pl"; } } WIZARD_SCRIPT_ARGUMENTS { baud = "115200"; data_bits = "8"; fixed_baud = "1"; parity = "N"; stop_bits = "1"; use_cts_rts = "0"; use_eop_register = "0"; sim_true_baud = "0"; sim_char_stream = ""; } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart_0.v"; Synthesis_Only_Files = ""; } } MODULE timer_1 { class = "altera_avalon_timer"; class_version = "5.1"; iss_model_name = "altera_avalon_timer"; SLAVE s1 { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Is_Printable_Device = "0"; Address_Alignment = "native"; Address_Width = "3"; Data_Width = "16"; Has_IRQ = "1"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "3"; } Base_Address = "0x00900060"; Address_Group = "0"; } PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "3"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "16"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "16"; } } } SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = "Timer with 1 ms timeout period."; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { always_run = "0"; fixed_period = "0"; snapshot = "1"; period = "1"; period_units = "ms"; reset_output = "0"; timeout_pulse_output = "0"; mult = "0.001"; } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_1.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } } MODULE lcd_16207_0 { class = "altera_avalon_lcd_16207"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd_16207_0.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT LCD_data { direction = "inout"; width = "8"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,"; } } PORT LCD_E { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT LCD_RS { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } PORT LCD_RW { direction = "output"; width = "1"; Is_Enabled = "1"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment"; pin_assignment = ""; } } } SLAVE control_slave { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT begintransfer { Is_Enabled = "1"; direction = "input"; type = "begintransfer"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT read { Is_Enabled = "1"; direction = "input"; type = "read"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "8"; } PORT write { Is_Enabled = "1"; direction = "input"; type = "write"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "8"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Is_Printable_Device = "1"; Address_Width = "2"; Data_Width = "8"; Base_Address = "0x00900030"; Address_Alignment = "native"; Read_Wait_States = "250ns"; Write_Wait_States = "250ns"; Setup_Time = "250ns"; Hold_Time = "250ns"; Read_Latency = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Top_Level_Ports_Are_Enumerated = "1"; View { Is_Collapsed = "1"; MESSAGES { } } Clock_Source = "clk"; } WIZARD_SCRIPT_ARGUMENTS { } } MODULE led_green { class = "altera_avalon_pio"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_green.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT in_port { direction = "input"; Is_Enabled = "0"; width = "9"; } PORT out_port { direction = "output"; Is_Enabled = "1"; width = "9"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,"; } } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "9"; } } SLAVE s1 { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "9"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Address_Width = "2"; Data_Width = "9"; Base_Address = "0x009000C0"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = " 9-bit PIO using
output pins"; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "1"; has_in = "0"; capture = "0"; edge_type = "NONE"; irq_type = "NONE"; } } MODULE led_red { class = "altera_avalon_pio"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/led_red.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT in_port { direction = "input"; Is_Enabled = "0"; width = "18"; } PORT out_port { direction = "output"; Is_Enabled = "1"; width = "18"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,,,,,,,,,,"; } } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "18"; } } SLAVE s1 { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "18"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Address_Width = "2"; Data_Width = "18"; Base_Address = "0x009000D0"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = " 18-bit PIO using
output pins"; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "1"; has_in = "0"; capture = "0"; edge_type = "NONE"; irq_type = "NONE"; } } MODULE button_pio { class = "altera_avalon_pio"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/button_pio.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT in_port { direction = "input"; Is_Enabled = "1"; width = "4"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,"; } } PORT out_port { direction = "output"; Is_Enabled = "0"; width = "4"; } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "4"; } } SLAVE s1 { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "4"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "4"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "1"; Address_Width = "2"; Data_Width = "4"; Base_Address = "0x00900120"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "5"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = " 4-bit PIO using
input pins with edge type FALLING and interrupt source EDGE "; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "0"; has_in = "1"; capture = "1"; edge_type = "FALLING"; irq_type = "EDGE"; } } MODULE switch_pio { class = "altera_avalon_pio"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/switch_pio.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT in_port { direction = "input"; Is_Enabled = "1"; width = "18"; originally_shared = "0"; is_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,,,,,,,,,,,"; } } PORT out_port { direction = "output"; Is_Enabled = "0"; width = "18"; } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "18"; } } SLAVE s1 { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "18"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Address_Width = "2"; Data_Width = "18"; Base_Address = "0x00900130"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = " 18-bit PIO using
input pins with edge type NONE and interrupt source NONE "; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "0"; has_in = "1"; capture = "0"; edge_type = "NONE"; irq_type = "NONE"; } } MODULE SEG7_Display { class = "user_logic_SEG7_LUT_8"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "0"; Data_Width = "32"; Has_IRQ = "0"; Has_Base_Address = "1"; Read_Wait_States = "0ns"; Write_Wait_States = "0ns"; Setup_Time = "0ns"; Hold_Time = "0ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00900028"; Address_Group = "0"; } PORT_WIRING { PORT oSEG0 { width = "7"; direction = "output"; type = "export"; } PORT oSEG1 { width = "7"; direction = "output"; type = "export"; } PORT oSEG2 { width = "7"; direction = "output"; type = "export"; } PORT oSEG3 { width = "7"; direction = "output"; type = "export"; } PORT oSEG4 { width = "7"; direction = "output"; type = "export"; } PORT oSEG5 { width = "7"; direction = "output"; type = "export"; } PORT oSEG6 { width = "7"; direction = "output"; type = "export"; } PORT oSEG7 { width = "7"; direction = "output"; type = "export"; } PORT iDIG { width = "32"; direction = "input"; type = "writedata"; } PORT iWR { width = "1"; direction = "input"; type = "write"; } PORT iCLK { width = "1"; direction = "input"; type = "clk"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "oSEG0"; radix = "hexadecimal"; } SIGNAL b { name = "oSEG1"; radix = "hexadecimal"; } SIGNAL c { name = "oSEG2"; radix = "hexadecimal"; } SIGNAL d { name = "oSEG3"; radix = "hexadecimal"; } SIGNAL e { name = "oSEG4"; radix = "hexadecimal"; } SIGNAL f { name = "oSEG5"; radix = "hexadecimal"; } SIGNAL g { name = "oSEG6"; radix = "hexadecimal"; } SIGNAL h { name = "oSEG7"; radix = "hexadecimal"; } SIGNAL i { name = "iDIG"; radix = "hexadecimal"; } SIGNAL j { name = "iWR"; } SIGNAL k { name = "iCLK"; } SIGNAL l { name = "iRST_N"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SEG7_LUT.v,__PROJECT_DIRECTORY__/SEG7_LUT_8.v, __PROJECT_DIRECTORY__/SEG7_Display.v"; } } MODULE sram_0 { class = "user_logic_SRAM_16Bits_512K"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "dynamic"; Address_Width = "18"; Data_Width = "16"; Has_IRQ = "0"; Has_Base_Address = "1"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; Is_Memory_Device = "1"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00980000"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } PORT_WIRING { PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT iADDR { width = "18"; direction = "input"; type = "address"; } PORT iWE_N { width = "1"; direction = "input"; type = "write_n"; } PORT iOE_N { width = "1"; direction = "input"; type = "outputenable_n"; } PORT iCE_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT iUB_N { width = "1"; direction = "input"; type = "byteenable_n"; } PORT iLB_N { width = "1"; direction = "input"; type = "byteenable_n"; } PORT SRAM_DQ { width = "16"; direction = "inout"; type = "export"; } PORT SRAM_ADDR { width = "18"; direction = "output"; type = "export"; } PORT SRAM_UB_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_LB_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_WE_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_CE_N { width = "1"; direction = "output"; type = "export"; } PORT SRAM_OE_N { width = "1"; direction = "output"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "oDATA"; radix = "hexadecimal"; } SIGNAL b { name = "iDATA"; radix = "hexadecimal"; } SIGNAL c { name = "iADDR"; radix = "hexadecimal"; } SIGNAL d { name = "iWE_N"; } SIGNAL e { name = "iOE_N"; } SIGNAL f { name = "iCE_N"; } SIGNAL g { name = "iRST_N"; } SIGNAL h { name = "iUB_N"; } SIGNAL i { name = "iLB_N"; } SIGNAL j { name = "SRAM_DQ"; radix = "hexadecimal"; } SIGNAL k { name = "SRAM_ADDR"; radix = "hexadecimal"; } SIGNAL l { name = "SRAM_UB_N"; } SIGNAL m { name = "SRAM_LB_N"; } SIGNAL n { name = "SRAM_WE_N"; } SIGNAL o { name = "SRAM_CE_N"; } SIGNAL p { name = "SRAM_OE_N"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SRAM_16Bit_512K.v, __PROJECT_DIRECTORY__/sram_0.v"; } } MODULE I2C_0 { class = "user_logic_Open_I2C"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "3"; Data_Width = "8"; Has_IRQ = "1"; Has_Base_Address = "1"; Read_Wait_States = "peripheral_controlled"; Write_Wait_States = "peripheral_controlled"; Setup_Time = "0"; Hold_Time = "0"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "6"; } Base_Address = "0x00900100"; Address_Group = "0"; } PORT_WIRING { PORT wb_clk_i { width = "1"; direction = "input"; type = "clk"; } PORT wb_rst_i { width = "1"; direction = "input"; type = "always0"; } PORT arst_i { width = "1"; direction = "input"; type = "reset_n"; } PORT wb_adr_i { width = "3"; direction = "input"; type = "address"; } PORT wb_dat_i { width = "8"; direction = "input"; type = "writedata"; } PORT wb_dat_o { width = "8"; direction = "output"; type = "readdata"; } PORT wb_we_i { width = "1"; direction = "input"; type = "write"; } PORT wb_stb_i { width = "1"; direction = "input"; type = "chipselect"; } PORT wb_cyc_i { width = "1"; direction = "input"; type = "chipselect"; } PORT wb_ack_o { width = "1"; direction = "output"; type = "waitrequest_n"; } PORT wb_inta_o { width = "1"; direction = "output"; type = "irq"; } PORT scl_pad_i { width = "1"; direction = "input"; type = "export"; } PORT scl_pad_o { width = "1"; direction = "output"; type = "export"; } PORT scl_padoen_o { width = "1"; direction = "output"; type = "export"; } PORT sda_pad_i { width = "1"; direction = "input"; type = "export"; } PORT sda_pad_o { width = "1"; direction = "output"; type = "export"; } PORT sda_padoen_o { width = "1"; direction = "output"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "wb_clk_i"; } SIGNAL b { name = "wb_rst_i"; } SIGNAL c { name = "arst_i"; } SIGNAL d { name = "wb_adr_i"; radix = "hexadecimal"; } SIGNAL e { name = "wb_dat_i"; radix = "hexadecimal"; } SIGNAL f { name = "wb_dat_o"; radix = "hexadecimal"; } SIGNAL g { name = "wb_we_i"; } SIGNAL h { name = "wb_stb_i"; } SIGNAL i { name = "wb_cyc_i"; } SIGNAL j { name = "wb_ack_o"; } SIGNAL k { name = "wb_inta_o"; } SIGNAL l { name = "scl_pad_i"; } SIGNAL m { name = "scl_pad_o"; } SIGNAL n { name = "scl_padoen_o"; } SIGNAL o { name = "sda_pad_i"; } SIGNAL p { name = "sda_pad_o"; } SIGNAL q { name = "sda_padoen_o"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/i2c_master_bit_ctrl.v,__PROJECT_DIRECTORY__/i2c_master_byte_ctrl.v,__PROJECT_DIRECTORY__/i2c_master_defines.v,__PROJECT_DIRECTORY__/i2c_master_top.v, __PROJECT_DIRECTORY__/I2C_0.v"; } } MODULE epcs_controller { class = "altera_avalon_epcs_flash_controller"; class_version = "5.1"; SLAVE epcs_control_port { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Is_Nonvolatile_Storage = "1"; Is_Printable_Device = "0"; Address_Alignment = "dynamic"; Is_Memory_Device = "1"; Address_Width = "9"; Data_Width = "32"; Has_IRQ = "1"; Read_Wait_States = "1"; Write_Wait_States = "1"; Base_Address = "0x00900800"; Address_Group = "0"; MASTERED_BY cpu_0/instruction_master { priority = "1"; } MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "7"; } } WIZARD_SCRIPT_ARGUMENTS { class = "altera_avalon_epcs_flash_controller"; flash_reference_designator = "U30"; } PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "9"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT data_from_cpu { Is_Enabled = "0"; direction = "input"; type = "writedata"; width = "16"; } PORT data_to_cpu { Is_Enabled = "0"; direction = "output"; type = "readdata"; width = "16"; } PORT dataavailable { Is_Enabled = "1"; direction = "output"; type = "dataavailable"; width = "1"; } PORT endofpacket { Is_Enabled = "1"; direction = "output"; type = "endofpacket"; width = "1"; } PORT epcs_select { Is_Enabled = "0"; direction = "input"; type = "chipselect"; width = "1"; } PORT irq { Is_Enabled = "1"; direction = "output"; type = "irq"; width = "1"; } PORT mem_addr { Is_Enabled = "0"; direction = "input"; type = "address"; width = "3"; } PORT read_n { Is_Enabled = "1"; direction = "input"; type = "read_n"; width = "1"; } PORT readdata { Is_Enabled = "1"; direction = "output"; type = "readdata"; width = "32"; } PORT readyfordata { Is_Enabled = "1"; direction = "output"; type = "readyfordata"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "32"; } } } SYSTEM_BUILDER_INFO { Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXII,STRATIXIIGX"; Fixed_Module_Name = "epcs_controller"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { databits = "8"; targetclock = "20"; clockunits = "MHz"; clockmult = "1000000"; numslaves = "1"; ismaster = "1"; clockpolarity = "0"; clockphase = "0"; lsbfirst = "0"; extradelay = "1"; targetssdelay = "100"; delayunits = "us"; delaymult = "1e-006"; prefix = "epcs_"; register_offset = "0x200"; MAKE { MACRO { EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)"; EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)"; EPCS_RELOCATE = "$(EPCS_RELOCATE_TMP:1=--relocate)"; EPCS_RELOCATE_TMP = "$(BOOTS_FROM_EPCS:0=)"; } MASTER cpu_0 { MACRO { BOOTS_FROM_EPCS = "0"; BOOT_COPIER_EPCS = "boot_loader_epcs.srec"; CPU_CLASS = "altera_nios2"; CPU_RESET_ADDRESS = "0x2000000"; } } TARGET delete_placeholder_warning { epcs_controller { Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt"; Is_Phony = "1"; Target_File = "do_delete_placeholder_warning"; } } TARGET flashfiles { epcs_controller { Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash=U30 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi"; Dependency = "$(ELF)"; Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash"; } } TARGET programflash { epcs_controller { All_Depends_On = "0"; Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir de2 $(QUARTUS_PROJECT_DIR))/ $(JTAG_CABLE) --epcs ; fi"; Dependency = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash"; Is_Phony = "1"; Target_File = "epcs_controller_boot_rom_programflash"; } } TARGET programflashnoelfdependency { epcs_controller { All_Depends_On = "0"; Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir de2 $(QUARTUS_PROJECT_DIR))/ $(JTAG_CABLE) --epcs ; fi"; Is_Phony = "1"; Target_File = "epcs_controller_boot_rom_programflashnoelf"; } } TARGET sim { epcs_controller { Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi"; Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)"; Command3 = "touch $(SIMDIR)/dummy_file"; Dependency = "$(ELF)"; Target_File = "$(SIMDIR)/dummy_file"; } } TARGET FPGA_HW { epcs_controller { All_Depends_On = "0"; Command1 = "sof2flash --flash=U30 --offset=0x00000000 --output=FPGA_HW.flash $(SOF) --epcs "; Command2 = "nios2-flash-programmer --input=FPGA_HW.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir de2 $(QUARTUS_PROJECT_DIR))/ $(JTAG_CABLE) --epcs $(EPCS_RELOCATE) "; Dependency = ""; Is_Phony = "1"; Target_File = "epcs_controller_boot_rom_FPGA_HW_configuration"; } } } clockunit = "kHz"; delayunit = "us"; } HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.v"; Synthesis_Only_Files = ""; } PORT_WIRING { } } MODULE ISP1362 { class = "altera_avalon_user_defined_interface"; class_version = "5.1"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Imported_Wait = "0"; Nios_Gen_Waits = "1"; Simulate_Imported_HDL = "1"; Port_Type = "Avalon Slave"; HDL_Import = "1"; Timing_Units = "ns"; Unit_Multiplier = "1"; Setup_Value = "200"; Hold_Value = "200"; Wait_Value = "100"; Address_Width = "32"; Module_List = ""; Show_Streaming = "0"; Show_Latency = "0"; Technology = "User Logic"; File_Count = "1"; Port_Count = "22"; Component_Desc = "ISP1362"; Module_Name = "ISP1362_IF"; } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "2"; Data_Width = "16"; Has_IRQ = "1"; Base_Address = "0x00900080"; Has_Base_Address = "1"; Read_Wait_States = "100ns"; Write_Wait_States = "100ns"; Setup_Time = "200ns"; Hold_Time = "200ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } IRQ_MASTER cpu_0/data_master { IRQ_Number = "4"; } Address_Group = "0"; IRQ_Number = "N/A"; } PORT_WIRING { PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iADDR { width = "2"; direction = "input"; type = "address"; } PORT iRD_N { width = "1"; direction = "input"; type = "read_n"; } PORT iWR_N { width = "1"; direction = "input"; type = "write_n"; } PORT iCS_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT OTG_DATA { width = "16"; direction = "inout"; type = "export"; } PORT OTG_ADDR { width = "2"; direction = "output"; type = "export"; } PORT OTG_RD_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_WR_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_CS_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_RST_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_DWKUP { width = "1"; direction = "output"; type = "export"; } PORT OTG_HWKUP { width = "1"; direction = "output"; type = "export"; } PORT OTG_INT0 { width = "1"; direction = "input"; type = "export"; } PORT OTG_INT1 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DREQ0 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DREQ1 { width = "1"; direction = "input"; type = "export"; } PORT OTG_DACK0_N { width = "1"; direction = "output"; type = "export"; } PORT OTG_DACK1_N { width = "1"; direction = "output"; type = "export"; } PORT oINT { width = "1"; direction = "output"; type = "irq_n"; } } } MASTER avalonM { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Data_Width = "32"; Address_Width = "8"; Max_Address_Width = "32"; Is_Enabled = "0"; } } SLAVE ahbS { SYSTEM_BUILDER_INFO { Bus_Type = "AHB"; Has_IRQ = "0"; Has_Base_Address = "1"; Address_Width = "10"; Data_Width = "32"; Base_Address = "--unknown--"; Address_Alignment = "native"; Read_Wait_States = "0"; Write_Wait_States = "0"; Is_Enabled = "0"; IRQ_Number = "N/A"; } } MASTER ahbM { SYSTEM_BUILDER_INFO { Bus_Type = "AHB"; Address_Width = "32"; Max_Address_Width = "32"; Data_Width = "32"; Interrupts_Enabled = "1"; Irq_Scheme = "Individual_requests"; Is_Enabled = "0"; } } HDL_INFO { Imported_HDL_Files = "./ISP1362_IF.v"; Synthesis_HDL_Files = "./ISP1362_IF.v,__PROJECT_DIRECTORY__/ISP1362.v"; } } MODULE VGA_0 { class = "user_logic_VGA_Controller"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "19"; Data_Width = "16"; Has_IRQ = "0"; Has_Base_Address = "1"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00A00000"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } Address_Group = "0"; } PORT_WIRING { PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iADDR { width = "19"; direction = "input"; type = "address"; } PORT iWR { width = "1"; direction = "input"; type = "write"; } PORT iRD { width = "1"; direction = "input"; type = "read"; } PORT iCS { width = "1"; direction = "input"; type = "chipselect"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT iCLK { width = "1"; direction = "input"; type = "clk"; } PORT VGA_R { width = "10"; direction = "output"; type = "export"; } PORT VGA_G { width = "10"; direction = "output"; type = "export"; } PORT VGA_B { width = "10"; direction = "output"; type = "export"; } PORT VGA_HS { width = "1"; direction = "output"; type = "export"; } PORT VGA_VS { width = "1"; direction = "output"; type = "export"; } PORT VGA_SYNC { width = "1"; direction = "output"; type = "export"; } PORT VGA_BLANK { width = "1"; direction = "output"; type = "export"; } PORT VGA_CLK { width = "1"; direction = "output"; type = "export"; } PORT iCLK_27 { width = "1"; direction = "input"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "iDATA"; radix = "hexadecimal"; } SIGNAL b { name = "oDATA"; radix = "hexadecimal"; } SIGNAL c { name = "iADDR"; radix = "hexadecimal"; } SIGNAL d { name = "iWR"; } SIGNAL e { name = "iRD"; } SIGNAL f { name = "iCS"; } SIGNAL g { name = "iRST_N"; } SIGNAL h { name = "iCLK"; } SIGNAL i { name = "VGA_R"; radix = "hexadecimal"; } SIGNAL j { name = "VGA_G"; radix = "hexadecimal"; } SIGNAL k { name = "VGA_B"; radix = "hexadecimal"; } SIGNAL l { name = "VGA_HS"; } SIGNAL m { name = "VGA_VS"; } SIGNAL n { name = "VGA_SYNC"; } SIGNAL o { name = "VGA_BLANK"; } SIGNAL p { name = "VGA_CLK"; } SIGNAL q { name = "iCLK_27"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Img_RAM.v,__PROJECT_DIRECTORY__/VGA_Controller.v,__PROJECT_DIRECTORY__/VGA_NIOS_CTRL.v,__PROJECT_DIRECTORY__/VGA_OSD_RAM.v,__PROJECT_DIRECTORY__/VGA_PLL.v, __PROJECT_DIRECTORY__/VGA_0.v"; } } MODULE dm9000 { class = "user_logic_DM9000A"; class_version = "2.0"; SYSTEM_BUILDER_INFO { Instantiate_In_System_Module = "1"; Is_Enabled = "1"; Date_Modified = "--unknown--"; Clock_Source = "clk"; View { Is_Collapsed = "1"; MESSAGES { } } } WIZARD_SCRIPT_ARGUMENTS { } SLAVE avalonS { SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Address_Alignment = "native"; Address_Width = "1"; Data_Width = "16"; Has_IRQ = "1"; Has_Base_Address = "1"; Read_Wait_States = "20ns"; Write_Wait_States = "20ns"; Setup_Time = "20ns"; Hold_Time = "20ns"; Is_Memory_Device = "0"; Uses_Tri_State_Data_Bus = "0"; Is_Enabled = "1"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "8"; } MASTERED_BY cpu_0/data_master { priority = "1"; } Base_Address = "0x00900090"; Address_Group = "0"; } PORT_WIRING { PORT iDATA { width = "16"; direction = "input"; type = "writedata"; } PORT oDATA { width = "16"; direction = "output"; type = "readdata"; } PORT iCMD { width = "1"; direction = "input"; type = "address"; } PORT iRD_N { width = "1"; direction = "input"; type = "read_n"; } PORT iWR_N { width = "1"; direction = "input"; type = "write_n"; } PORT iCS_N { width = "1"; direction = "input"; type = "chipselect_n"; } PORT iRST_N { width = "1"; direction = "input"; type = "reset_n"; } PORT oINT { width = "1"; direction = "output"; type = "irq"; } PORT ENET_DATA { width = "16"; direction = "inout"; type = "export"; } PORT ENET_CMD { width = "1"; direction = "output"; type = "export"; } PORT ENET_RD_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_WR_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_CS_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_RST_N { width = "1"; direction = "output"; type = "export"; } PORT ENET_INT { width = "1"; direction = "input"; type = "export"; } } } SIMULATION { DISPLAY { SIGNAL a { name = "iDATA"; radix = "hexadecimal"; } SIGNAL b { name = "oDATA"; radix = "hexadecimal"; } SIGNAL c { name = "iCMD"; } SIGNAL d { name = "iRD_N"; } SIGNAL e { name = "iWR_N"; } SIGNAL f { name = "iCS_N"; } SIGNAL g { name = "iRST_N"; } SIGNAL h { name = "oINT"; } SIGNAL i { name = "ENET_DATA"; radix = "hexadecimal"; } SIGNAL j { name = "ENET_CMD"; } SIGNAL k { name = "ENET_RD_N"; } SIGNAL l { name = "ENET_WR_N"; } SIGNAL m { name = "ENET_CS_N"; } SIGNAL n { name = "ENET_RST_N"; } SIGNAL o { name = "ENET_INT"; } } } HDL_INFO { Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/DM9000A_IF.v, __PROJECT_DIRECTORY__/dm9000.v"; } } MODULE debug_pins { class = "altera_avalon_pio"; class_version = "5.1"; HDL_INFO { Precompiled_Simulation_Library_Files = ""; Simulation_HDL_Files = ""; Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/debug_pins.v"; Synthesis_Only_Files = ""; } PORT_WIRING { PORT in_port { direction = "input"; Is_Enabled = "0"; width = "8"; } PORT out_port { direction = "output"; Is_Enabled = "1"; width = "8"; originally_shared = "0"; BOARD_COMPONENT de2 { component_pin = "use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment,use_quartus_pin_assignment"; pin_assignment = ",,,,,,,"; } is_shared = "0"; } PORT bidir_port { direction = "inout"; Is_Enabled = "0"; width = "8"; } } SLAVE s1 { PORT_WIRING { PORT address { Is_Enabled = "1"; direction = "input"; type = "address"; width = "2"; } PORT chipselect { Is_Enabled = "1"; direction = "input"; type = "chipselect"; width = "1"; } PORT clk { Is_Enabled = "1"; direction = "input"; type = "clk"; width = "1"; } PORT reset_n { Is_Enabled = "1"; direction = "input"; type = "reset_n"; width = "1"; } PORT write_n { Is_Enabled = "1"; direction = "input"; type = "write_n"; width = "1"; } PORT writedata { Is_Enabled = "1"; direction = "input"; type = "writedata"; width = "8"; } } SYSTEM_BUILDER_INFO { Bus_Type = "avalon"; Has_IRQ = "0"; Address_Width = "2"; Data_Width = "8"; Base_Address = "0x00800000"; Address_Alignment = "native"; Read_Wait_States = "1"; Write_Wait_States = "0"; Is_Readable = "0"; Is_Writable = "1"; MASTERED_BY cpu_0/data_master { priority = "1"; } Address_Group = "0"; IRQ_MASTER cpu_0/data_master { IRQ_Number = "NC"; } IRQ_Number = "N/A"; } } SYSTEM_BUILDER_INFO { Date_Modified = ""; Is_Enabled = "1"; Instantiate_In_System_Module = "1"; Wire_Test_Bench_Values = "1"; Top_Level_Ports_Are_Enumerated = "1"; Clock_Source = "clk"; View { Settings_Summary = " 8-bit PIO using
output pins"; MESSAGES { } Is_Collapsed = "1"; } } WIZARD_SCRIPT_ARGUMENTS { Do_Test_Bench_Wiring = "0"; Driven_Sim_Value = "0x0000"; has_tri = "0"; has_out = "1"; has_in = "0"; capture = "0"; edge_type = "NONE"; irq_type = "NONE"; } } }